ASIC Design Verification Consulting
Greg White - BSEE
20 years experience in ASIC and FPGA Circuit Design and Design Verification
Specializing in Digital Logic Verification of Integrated Circuits and Core IPs
Since 2007 I have specialized in verification of digital designs using simulation and emulation tools. Prior to that my project emphasis was spread among Design, Synthesis and Verification of Digital and Mixed Signal devices and IPs. Ran Verilog and VHDL training workshops for engineers.
- Constructed a complete SystemVerilog testbench from scratch to successfully validate an ASIC with complete functional and high toggle coverage.
- Improved and modified test benches comprising largely SystemVerilog with UVM and OVM. Included writing constrained random and directed tests, sequences, checkers, scoreboards, onitors.
- Performance based testing of L2 Cache for a MIPs processor
- Interaction with designers to achieve full functional and toggle coverage
- Design of test plans, test specs
- Full regression testing
- SOIC Emulation
- Design debugging based on verification
- Full system SOIC simulation
- Gate level simulation with timing backannotation to netlist
- Static timing analysis
- Equivalency checking
Analog and Mixed Signal Design and Verification
- Successfully verified a mixed signal image sensor comprising a large array of A/D cells. SystemVerilog with analog behavioral models.
- Designed and Synthesized Delta-Sigma Modulator for driving analog transistors in a mixed signal ASIC using C and VHDL modeling.
- TDMA (Time Division Multiple Access)Modulators/Demodulators
- High Speed Clock/Data Synchronization
- Tone Generators, Detectors
- Phase Locked Loops
- Injection locked oscillators
Prior to 2007 my consulting work had more emphasis on Digital Design:
- DSP Design for audio applications
- 3D Video Graphics ASIC: Designed Matrix and Vector Generator modules
- 2D Video Graphics ASIC for Heads-Up Display: Designed Mux and Vector Graphics modules
- Synthesis of L2 cache for superscalar 64 bit Sparc based RISC prodessor.
- Redesign of 32 bit MIPs based RISC processor
HDL Training Workshops
Have led Applied Verilog and VHDL four and five day workshops for engineers. The goal of these trainings was to ensure the trainees had enough of a working knowledge of the language and tools to make immediate contributions.
HARDWARE DESIGN (HDL) LANGUAGES
- System Verilog with OVM and VMM class libraries
- VERA with RVM class libraries
- VHDL with C interface
- Synopsys DC Shell
- Verisity e (Specman)
- Verilog with PLI and VPI - VCS, Verilog-XL, NCSim, ICCR, Modelsim
- Wrote an assembler language for programming a CDC bus interface simulator
- Z80 assembler
- 8085 assembler
- 8051 assembler
- AMD 2900 microcode