Clients include

ASIC Design Verification Consulting
Greg White - BSEE

20 years experience in ASIC and FPGA Circuit Design and Design Verification
US Citizen

Specializing in Digital Logic Verification of Integrated Circuits and Core IPs


Since 2007 I have specialized in verification of digital designs using simulation and emulation tools. Prior to that my project emphasis was spread among Design, Synthesis and Verification of Digital and Mixed Signal devices and IPs. Ran Verilog and VHDL training workshops for engineers.

Digital Verification

Analog and Mixed Signal Design and Verification

Digital Design

Prior to 2007 my consulting work had more emphasis on Digital Design:

HDL Training Workshops

Have led Applied Verilog and VHDL four and five day workshops for engineers. The goal of these trainings was to ensure the trainees had enough of a working knowledge of the language and tools to make immediate contributions.



Open Verification Methodology
System Verilog