ASIC Design Verification Consulting
Greg White - BSEE
20 years experience in ASIC and FPGA Circuit Design and Design Verification
I've been Consulting in ASIC/FPGA Design and Verification since 1987
Here is a summary of some of my work:
- Implemented constrained random and directed testing of 3 ICs which are part of a 100G optical router, utilizing System Verilog with RVM, and Specman
- Coopted strategies to improve toggle and code coverage, thereby assuring successful design functionality
- Expanded test environment to rigorously validate new features and design alterations while maintaining comprehensive regression testing
- Accomodated last minute changes to IC designs to assure continually robust visibility of the design and coverage.
Space Systems Loral
- Creation and implementation of verification test bench and methodology for verifying Telemetry Encoder IC for high speed commercial satellite communication with CRC and Reed-Solomon checking.
- Utilized constrained-random and directed tests to converge on high toggle coverage and functional coverage.
- Interfaced resultant test bench with lab prototypes, using object oriented System Verilog with OVM and SVA Assertions.
- Extensive documentation and presentations.
- Verification of Command Control Unit system IC for onboard satellite applications, utilizing compact PCI and MBUS interfaces.
- Assembler programming of proprietary modules.
Verification of PATA and SATA ATAPI drive interface ASIC for consumer multimedia product. Utilized System Verilog SVA Assertions.
Development of Verification IP for telecommunications ICs using Object Oriented Vera with RVM libraries, as part of a high speed wireless DSP modem for cellular telephone applications.
Design and verification, synthesis and system integration of a digital IC for Credence's Kalos high performance IC tester which controlled several analog ICs, thereby revolutionizing Credence's tester architecture.
- RTL and behavioral logic design
- Gate Synthesis
- RTL and Gate simulation and debugging
- Built test benches
- Generated test methodology
- generated specifications
- created several presentations to management and engineers
Verification of a cellular phone controller chip for controlling antenna selection based on signal quality.
Design, verification and synthesis of Digital to Analog Converter, part of of mixed signal SOIC chip used in next generation IPODs and other MP3 players.
- Complex arithmetic design against bit-exact C system modeling.
- Designed and verified Sigma-Delta Modulator, DSP(Digital Signal Processor), FIR filters with ALU and FIFO using VERA, NCSim, PERL and in-house verification tools.
- Interfaced with transistor level analog drivers.
- Optimized for low power consumption.
- Logic verification of MP3 Digital audio control circuitry in IC.
Cadence Design Systems
Worked directly with Cadence's client base and their ASIC design projects, comprising a wide range of chip designs to resolve problems. These projects represent a large portion of the VLSI industry. I solved logic design, verification and synthesis problems and problems such as timing signoff. I would often correct and streamline methodologies which had been in place. This involved a wide range of tools including NCSim, Verilog-XL, Leapfrog, Synopsys, C++, PERL PLI, VPI and other scripting languages, equivalency check tools and VHDL C interface. Cleared up numerous issues including timing, race conditions, and a wide variety verification processes as well as problems involved with interfacing EDA tools with each other.
Electronics for Imaging
Design and Verification of ATA-66 IDE interface ASIC, which interfaces with a PCI bus, for a printer interface utilizing Verilog and a Verilog testbench, integrating two IP cores. Wrote specifications.
Worked with a team to design a high end 3D Graphics ASIC. Designed a video/graphics mixer on the chip using VHDL while verifying an arithmetic matrix unit of the IC using a C++/VHDL testbench.
Used Timemill to verify performance of their vendor.s memory models (Nurlogic).
Wrote Verilog tasks and synthesized with Synopsys to verify and optimize the performance of a secondary memory cache unit of a superscalar 64 bit Sparc compatible RISC processor. This involved finding weaknesses in the cache scheme which would otherwise slow down the processor. Also performed synthesis on this full-custom design, altering timing and area constraints in order to converge on desired performance.
Designed and synthesized, with VHDL, a high speed telecommunications ASIC utilizing ATM Utopia bus and TDMA protocols. Interfaced with codecs and Multi-Vendor Integration Protocol Bus and PCI Bus.
Design verification of ASICs used in VHDL based hardware accelerator used for ASIC emulation
I ran instructional classes for Verilog and VHDL applications to Design and Verification engineers throughout North America.
Lead the redesign 32 bit RISC processor ASIC. When I started this project, the original designers were not available and Lockheed had been forced to change ASIC vendors. I worked with the computer architect to successfully reconstruct and test the processor. Used VHDL with Synopsys design compiler with JTAG insertion and built-in testing and successfully taped the chip out.
Worked with a team designing a heads-up avionics display system for the F18-EF fighter as well as the Comanche project. Wrote the high level specifications, designed on system and circuit levels, wrote a high level VHDL model and test bench (VHDL, sed, awk and C), wrote the RTL code model, synthesized, verified and successfully taped out to the vendor (LSI Logic. These ASICs were designed for video timing control and processing of high speed video and graphics video mixer for the avionics heads-up display with the video originating from a number of sources.
Design of FPGAs for wind generator controller .
Design and modeling of early RAID architecture.
Design of mixed signal ASICs for telephone headsets.
Design of ASICs for a Class 5 Telcom Switch.
Synopsys' Inner Circle consulting program.